The present invention relates to a ladder resistor circuit made from a multi-layered poly-crystalline silicon film and a semiconductor device comprising the ladder resistor, a transistor and a capacitor.
FIG. 31 is a process block diagram of a prior art manufacturing method for fabricating an insulated gate field effect transistor and a ladder resistor circuit used for a semiconductor device. At first, a gate oxide film of the insulated gate field effect transistor is formed (Step 107) and then the poly-crystalline silicon film is deposited by LPCVD (Step 108). This poly-crystalline silicon film is formed so as to have a thickness from 2000 A to 4000 A to use as a gate electrode of the MISFET. Next, in order to determine a resistance value of the poly-crystalline silicon, an impurity having a concentration of 10.sup.15 to 5.times.10.sup.19 atoms/cm.sup.3 is ion-implanted (Step 109). Then, a high-concentrate impurity is implanted to parts of the poly-crystalline silicon film by means of thermal diffusion in 850 to 950.degree. C. (Step 110). The concentration of this impurity is more than 10.sup.20 atoms/cm.sup.3 and a resistance value of the poly-crystalline silicon film per unit length and unit width, i.e. a sheet resistance, is as low as less than 100 .OMEGA./.quadrature.. It is implanted to the locations which require a low resistance, including a part where the gate electrode of the insulated gate field effect transistor is formed and a part for contacting with a metal wire at the edge of a high-resistance poly-crystalline silicon resistor having more than 1 k .OMEGA./.quadrature. of sheet resistance.
Next, this poly-crystalline silicon is patterned into shapes of a gate electrode, a resistor or the like (Step 111). Then, an impurity is implanted to a source/drain area of the insulated gate field effect transistor by means of ion implantation (Step 112). The concentration of the impurity is as high as more than 10.sup.20 atoms/cm.sup.3.
Next, an intermediate insulating film is formed on the poly-crystalline silicon (Step 113) and contact holes are created on the poly-crystalline silicon film and the substrate on which the source/drain is formed (Step 114). After that, metal wires for electrically connecting each part of the circuit are formed (Step 115). Generally, this metal wire is an aluminum wire.
However, the prior art ladder resistor circuit has had the following problems:
(1) When it is designed so as to have a large resistance value, the length of the resistor has to be prolonged in proportion to that. Due to that, the chip size becomes large, disallowing to supply a low cost circuit; and PA1 (2) If the gate electrode of the insulated gate field effect transistor and the thin film of the ladder resistor provided on the same substrate are to be formed in combination, the area of the ladder resistor becomes large, increasing the cost similarly.
Accordingly, in order to solve such problems of the prior art, the present invention aims at increasing a resistance value per unit area and along that, at miniaturizing a chip size, at lowering the cost, at increasing an accuracy and at integrating a transistor and a capacitor.